.. ************************************************** * * * Automatically generated file, do not edit! * * * ************************************************** ==================================================================================== Syntax of GFX12 Instructions ==================================================================================== .. contents:: :local: Introduction ============ This document describes the syntax of GFX12 instructions. Notation ======== Notation used in this document is explained :ref:`here`. Overview ======== An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document`. Instructions ============ SMEM ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_atc_probe :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_atc_probe_buffer :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b128 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b256 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b32 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b512 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b64 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_b96 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_i16 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_i8 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_u16 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_load_u8 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_nop :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_buffer_prefetch_data :ref:`sbase`, :ref:`ioffset`, :ref:`soffset`, :ref:`sdata` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_dcache_inv :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b128 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b256 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b32 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b512 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b64 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_b96 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_i16 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_i8 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_u16 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_load_u8 :ref:`sdata`, :ref:`sbase`, :ref:`soffset` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_prefetch_data :ref:`sbase`, :ref:`ioffset`, :ref:`soffset`, :ref:`sdata` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_prefetch_data_pc_rel :ref:`ioffset`, :ref:`soffset`, :ref:`sdata` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_prefetch_inst :ref:`sbase`, :ref:`ioffset`, :ref:`soffset`, :ref:`sdata` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` s_prefetch_inst_pc_rel :ref:`ioffset`, :ref:`soffset`, :ref:`sdata` :ref:`offset24s` :ref:`th` :ref:`scope` :ref:`nv` SOP1 ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_abs_i32 :ref:`sdst`, :ref:`ssrc0` s_alloc_vgpr :ref:`ssrc0` s_and_not0_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_and_not0_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_and_not0_wrexec_b32 :ref:`sdst`, :ref:`ssrc0` s_and_not0_wrexec_b64 :ref:`sdst`, :ref:`ssrc0` s_and_not1_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_and_not1_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_and_not1_wrexec_b32 :ref:`sdst`, :ref:`ssrc0` s_and_not1_wrexec_b64 :ref:`sdst`, :ref:`ssrc0` s_and_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_and_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_barrier_init :ref:`ssrc0` s_barrier_join :ref:`ssrc0` s_barrier_signal :ref:`ssrc0` s_barrier_signal_isfirst :ref:`ssrc0` s_bcnt0_i32_b32 :ref:`sdst`, :ref:`ssrc0` s_bcnt0_i32_b64 :ref:`sdst`, :ref:`ssrc0` s_bcnt1_i32_b32 :ref:`sdst`, :ref:`ssrc0` s_bcnt1_i32_b64 :ref:`sdst`, :ref:`ssrc0` s_bitreplicate_b64_b32 :ref:`sdst`, :ref:`ssrc0` s_bitset0_b32 :ref:`sdst`, :ref:`ssrc0` s_bitset0_b64 :ref:`sdst`, :ref:`ssrc0` s_bitset1_b32 :ref:`sdst`, :ref:`ssrc0` s_bitset1_b64 :ref:`sdst`, :ref:`ssrc0` s_brev_b32 :ref:`sdst`, :ref:`ssrc0` s_brev_b64 :ref:`sdst`, :ref:`ssrc0` s_ceil_f16 :ref:`sdst`, :ref:`ssrc0` s_ceil_f32 :ref:`sdst`, :ref:`ssrc0` s_cls_i32 :ref:`sdst`, :ref:`ssrc0` s_cls_i32_i64 :ref:`sdst`, :ref:`ssrc0` s_clz_i32_u32 :ref:`sdst`, :ref:`ssrc0` s_clz_i32_u64 :ref:`sdst`, :ref:`ssrc0` s_cmov_b32 :ref:`sdst`, :ref:`ssrc0` s_cmov_b64 :ref:`sdst`, :ref:`ssrc0` s_ctz_i32_b32 :ref:`sdst`, :ref:`ssrc0` s_ctz_i32_b64 :ref:`sdst`, :ref:`ssrc0` s_cvt_f16_f32 :ref:`sdst`, :ref:`ssrc0` s_cvt_f32_f16 :ref:`sdst`, :ref:`ssrc0` s_cvt_f32_i32 :ref:`sdst`, :ref:`ssrc0` s_cvt_f32_u32 :ref:`sdst`, :ref:`ssrc0` s_cvt_hi_f32_f16 :ref:`sdst`, :ref:`ssrc0` s_cvt_i32_f32 :ref:`sdst`, :ref:`ssrc0` s_cvt_u32_f32 :ref:`sdst`, :ref:`ssrc0` s_floor_f16 :ref:`sdst`, :ref:`ssrc0` s_floor_f32 :ref:`sdst`, :ref:`ssrc0` s_get_barrier_state :ref:`sdst`, :ref:`ssrc0` s_get_lock_state :ref:`sdst`, :ref:`ssrc0` s_getpc_b64 :ref:`sdst` s_mov_b32 :ref:`sdst`, :ref:`ssrc0` s_mov_b64 :ref:`sdst`, :ref:`ssrc0` s_mov_fed_b32 :ref:`sdst`, :ref:`ssrc0` s_mov_from_global_b32 :ref:`sdst`, :ref:`ssrc0` s_mov_from_global_b64 :ref:`sdst`, :ref:`ssrc0` s_mov_regrd_b32 :ref:`sdst`, :ref:`ssrc0` s_mov_to_global_b32 :ref:`sdst`, :ref:`ssrc0` s_mov_to_global_b64 :ref:`sdst`, :ref:`ssrc0` s_movreld_b32 :ref:`sdst`, :ref:`ssrc0` s_movreld_b64 :ref:`sdst`, :ref:`ssrc0` s_movrels_b32 :ref:`sdst`, :ref:`ssrc0` s_movrels_b64 :ref:`sdst`, :ref:`ssrc0` s_movrelsd_2_b32 :ref:`sdst`, :ref:`ssrc0` s_nand_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_nand_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_nor_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_nor_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_not_b32 :ref:`sdst`, :ref:`ssrc0` s_not_b64 :ref:`sdst`, :ref:`ssrc0` s_or_not0_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_or_not0_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_or_not1_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_or_not1_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_or_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_or_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_quadmask_b32 :ref:`sdst`, :ref:`ssrc0` s_quadmask_b64 :ref:`sdst`, :ref:`ssrc0` s_rfe_b64 :ref:`ssrc0` s_rndne_f16 :ref:`sdst`, :ref:`ssrc0` s_rndne_f32 :ref:`sdst`, :ref:`ssrc0` s_sendmsg_rtn_b32 :ref:`sdst`, :ref:`ssrc0` s_sendmsg_rtn_b64 :ref:`sdst`, :ref:`ssrc0` s_setpc_b64 :ref:`ssrc0` s_sext_i32_i16 :ref:`sdst`, :ref:`ssrc0` s_sext_i32_i8 :ref:`sdst`, :ref:`ssrc0` s_sleep_var :ref:`ssrc0` s_swap_to_global_b32 :ref:`sdst`, :ref:`ssrc0` s_swappc_b64 :ref:`sdst`, :ref:`ssrc0` s_trunc_f16 :ref:`sdst`, :ref:`ssrc0` s_trunc_f32 :ref:`sdst`, :ref:`ssrc0` s_try_lock :ref:`ssrc0` s_unlock :ref:`ssrc0` s_wakeup_barrier :ref:`ssrc0` s_wqm_b32 :ref:`sdst`, :ref:`ssrc0` s_wqm_b64 :ref:`sdst`, :ref:`ssrc0` s_xnor_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_xnor_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` s_xor_saveexec_b32 :ref:`sdst`, :ref:`ssrc0` s_xor_saveexec_b64 :ref:`sdst`, :ref:`ssrc0` SOP2 ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_absdiff_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_co_ci_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_co_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_co_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_add_nc_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_and_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_and_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_and_not1_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_and_not1_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_ashr_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_ashr_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfe_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfe_i64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfe_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfe_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfm_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_bfm_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_cselect_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_cselect_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_cvt_pk_rtz_f16_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_fmaak_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1`, :ref:`literal` s_fmac_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_fmac_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_fmamk_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`literal`, :ref:`ssrc1` s_lshl1_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshl2_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshl3_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshl4_add_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshl_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshl_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshr_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_lshr_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_max_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_max_num_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_max_num_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_max_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_maximum_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_maximum_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_min_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_min_num_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_min_num_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_min_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_minimum_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_minimum_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_hi_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_hi_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_mul_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_nand_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_nand_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_nor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_nor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_or_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_or_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_or_not1_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_or_not1_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_pack_hh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_pack_hl_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_pack_lh_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_pack_ll_b32_b16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_co_ci_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_co_i32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_co_u32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_f16 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_f32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_sub_nc_u64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_xnor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_xnor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_xor_b32 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` s_xor_b64 :ref:`sdst`, :ref:`ssrc0`, :ref:`ssrc1` SOPC ---- .. parsed-literal:: **INSTRUCTION** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_bitcmp0_b32 :ref:`ssrc0`, :ref:`ssrc1` s_bitcmp0_b64 :ref:`ssrc0`, :ref:`ssrc1` s_bitcmp1_b32 :ref:`ssrc0`, :ref:`ssrc1` s_bitcmp1_b64 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_eq_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_eq_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_eq_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_eq_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_eq_u64 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ge_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ge_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ge_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ge_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_gt_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_gt_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_gt_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_gt_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_le_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_le_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_le_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_le_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lg_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lg_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lg_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lg_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lg_u64 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lt_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lt_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lt_i32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_lt_u32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_neq_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_neq_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nge_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nge_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ngt_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_ngt_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nle_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nle_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nlg_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nlg_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nlt_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_nlt_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_o_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_o_f32 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_u_f16 :ref:`ssrc0`, :ref:`ssrc1` s_cmp_u_f32 :ref:`ssrc0`, :ref:`ssrc1` SOPK ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_addk_co_i32 :ref:`sdst`, :ref:`simm16` s_call_b64 :ref:`sdst`, :ref:`simm16` s_cmovk_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_eq_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_eq_u32 :ref:`sdst`, :ref:`simm16` s_cmpk_ge_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_ge_u32 :ref:`sdst`, :ref:`simm16` s_cmpk_gt_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_gt_u32 :ref:`sdst`, :ref:`simm16` s_cmpk_le_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_le_u32 :ref:`sdst`, :ref:`simm16` s_cmpk_lg_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_lg_u32 :ref:`sdst`, :ref:`simm16` s_cmpk_lt_i32 :ref:`sdst`, :ref:`simm16` s_cmpk_lt_u32 :ref:`sdst`, :ref:`simm16` s_getreg_b32 :ref:`sdst`, :ref:`simm16` s_getreg_regrd_b32 :ref:`sdst`, :ref:`simm16` s_movk_i32 :ref:`sdst`, :ref:`simm16` s_mulk_i32 :ref:`sdst`, :ref:`simm16` s_setreg_b32 :ref:`simm16`, :ref:`sdst` s_setreg_imm32_b32 :ref:`simm16`, :ref:`literal` s_subvector_loop_begin :ref:`sdst`, :ref:`simm16` s_subvector_loop_end :ref:`sdst`, :ref:`simm16` s_version :ref:`simm16` SOPP ---- .. parsed-literal:: **INSTRUCTION** **SRC** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| s_barrier s_barrier_leave s_barrier_wait :ref:`simm16` s_branch :ref:`simm16` s_cbranch_cdbgsys :ref:`simm16` s_cbranch_cdbgsys_and_user :ref:`simm16` s_cbranch_cdbgsys_or_user :ref:`simm16` s_cbranch_cdbguser :ref:`simm16` s_cbranch_execnz :ref:`simm16` s_cbranch_execz :ref:`simm16` s_cbranch_scc0 :ref:`simm16` s_cbranch_scc1 :ref:`simm16` s_cbranch_vccnz :ref:`simm16` s_cbranch_vccz :ref:`simm16` s_clause :ref:`simm16` s_code_end s_decperflevel :ref:`simm16` s_delay_alu :ref:`simm16` s_denorm_mode :ref:`simm16` s_endpgm s_endpgm_ordered_ps_done s_endpgm_saved s_icache_inv s_incperflevel :ref:`simm16` s_nop :ref:`simm16` s_round_mode :ref:`simm16` s_sendmsg :ref:`simm16` s_sendmsghalt :ref:`simm16` s_set_inst_prefetch_distance :ref:`simm16` s_sethalt :ref:`simm16` s_setkill :ref:`simm16` s_setprio :ref:`simm16` s_singleuse_vdst :ref:`simm16` s_sleep :ref:`simm16` s_trap :ref:`simm16` s_ttracedata s_ttracedata_imm :ref:`simm16` s_wait_alu :ref:`simm16` s_wait_bvhcnt :ref:`simm16` s_wait_dscnt :ref:`simm16` s_wait_event :ref:`simm16` s_wait_expcnt :ref:`simm16` s_wait_idle s_wait_kmcnt :ref:`simm16` s_wait_loadcnt :ref:`simm16` s_wait_loadcnt_dscnt :ref:`simm16` s_wait_samplecnt :ref:`simm16` s_wait_storecnt :ref:`simm16` s_wait_storecnt_dscnt :ref:`simm16` s_waitcnt :ref:`simm16` s_wakeup VBUFFER ------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| buffer_atomic_add_f32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_add_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_add_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_and_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_and_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_cmpswap_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_cmpswap_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_cond_sub_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_dec_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_dec_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_inc_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_inc_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_max_i32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_max_i64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_max_num_f32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_max_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_max_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_min_i32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_min_i64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_min_num_f32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_min_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_min_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_or_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_or_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_pk_add_bf16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_pk_add_f16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_sub_clamp_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_sub_u32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_sub_u64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_swap_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_swap_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_xor_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_atomic_xor_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_gl0_inv :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_gl1_inv :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_b128 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_b96 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_block :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_hi_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_hi_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_hi_i8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_hi_u8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_i8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_d16_u8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_i16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_i8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_b32 :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_format_x :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_i16 :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_i8 :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_u16 :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_lds_u8 :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_u16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_load_u8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_nop :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b128 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b32 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b64 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_b96 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_block :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_hi_b16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_hi_b8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_d16_hi_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` buffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_load_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_d16_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_d16_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_d16_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_d16_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_format_x :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_format_xy :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_format_xyz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` tbuffer_store_format_xyzw :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`soffset` :ref:`offset` :ref:`idxen` :ref:`offen` :ref:`tfe` :ref:`th` :ref:`scope` :ref:`nv` VDS --- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| ds_add_f32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_f64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_rtn_f32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_add_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_and_b32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_and_b64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_and_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_and_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_append :ref:`vdst` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_fi_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_fi_from_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_fi_to_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_fi_to_simd_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_from_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_to_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bpermute_to_simd_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bvh_stack_push4_pop1_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bvh_stack_push8_pop1_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_bvh_stack_push8_pop2_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cmpstore_b32 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cmpstore_b64 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cmpstore_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cmpstore_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cond_sub_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_cond_sub_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_condxchg32_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_consume :ref:`vdst` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_dec_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_dec_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_dec_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_dec_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_inc_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_inc_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_inc_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_inc_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_2addr_b32 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_2addr_b64 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_2addr_stride64_b32 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_2addr_stride64_b64 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_addtid_b32 :ref:`vdst` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_b128 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_b32 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_b64 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_b96 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_i16 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_i8 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_i8_d16 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_i8_d16_hi :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u16 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u16_d16 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u16_d16_hi :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u8 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u8_d16 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_load_u8_d16_hi :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_i32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_i64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_num_f32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_num_f64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_num_rtn_f32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_num_rtn_f64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_rtn_i32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_rtn_i64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_max_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_i32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_i64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_num_f32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_num_f64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_num_rtn_f32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_num_rtn_f64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_rtn_i32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_rtn_i64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_min_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_mskor_b32 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_mskor_b64 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_mskor_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_mskor_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_nop :ref:`offset` :ref:`offset0` :ref:`offset1` ds_or_b32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_or_b64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_or_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_or_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_permute_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_permute_from_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_permute_to_global_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_permute_to_simd_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_pk_add_bf16 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_pk_add_f16 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_pk_add_rtn_bf16 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_pk_add_rtn_f16 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_rsub_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_rsub_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_rsub_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_rsub_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_2addr_b32 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_2addr_b64 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_2addr_stride64_b32 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_2addr_stride64_b64 :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_addtid_b32 :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b128 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b16 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b16_d16_hi :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b8 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b8_d16_hi :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_store_b96 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_2addr_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_2addr_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_2addr_stride64_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_2addr_stride64_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_storexchg_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_clamp_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_clamp_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_rtn_u32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_rtn_u64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_u32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_sub_u64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_swizzle_b32 :ref:`vdst`, :ref:`addr` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_wrap_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0`, :ref:`data1` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_xor_b32 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_xor_b64 :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_xor_rtn_b32 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` ds_xor_rtn_b64 :ref:`vdst`, :ref:`addr`, :ref:`data0` :ref:`offset` :ref:`offset0` :ref:`offset1` VDSDIR ------ .. parsed-literal:: **INSTRUCTION** **DST** **SRC** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| ds_direct_load :ref:`vdst` :ref:`wait_va_vdst` :ref:`wait_vdst` :ref:`wait_vm_vsrc` ds_param_load :ref:`vdst`, :ref:`attr` :ref:`wait_va_vdst` :ref:`wait_vdst` :ref:`wait_vm_vsrc` VERIF ----- .. parsed-literal:: **INSTRUCTION** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| fake_s_delay_alu fake_s_nop fake_s_wait_alu fake_s_wait_bvhcnt fake_s_wait_dscnt fake_s_wait_expcnt fake_s_wait_kmcnt fake_s_wait_loadcnt fake_s_wait_samplecnt fake_s_wait_storecnt fake_s_waitcnt fake_v_nop ill_0 ill_1 ill_beef metadata verif_s_adjdelay_alu VEXPORT ------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| export :ref:`tgt`, :ref:`vsrc0`, :ref:`vsrc1`, :ref:`vsrc2`, :ref:`vsrc3` :ref:`done` :ref:`row_en` VFLAT ----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| flat_atomic_add_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_add_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_add_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_and_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_and_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_cmpswap_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_cmpswap_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_cond_sub_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_dec_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_dec_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_inc_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_inc_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_max_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_max_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_max_num_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_max_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_max_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_min_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_min_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_min_num_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_min_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_min_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_or_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_or_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_pk_add_bf16 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_pk_add_f16 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_sub_clamp_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_sub_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_sub_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_swap_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_swap_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_xor_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_atomic_xor_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_b128 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_b32 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_b64 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_b96 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_b16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_d16_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_i16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_i8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_u16 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_load_u8 :ref:`vdst`, :ref:`vaddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b128 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b16 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b32 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b64 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b8 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_b96 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_d16_hi_b16 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` flat_store_d16_hi_b8 :ref:`vaddr`, :ref:`vsrc` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` VGLOBAL ------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| global_atomic_add_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_add_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_add_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_and_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_and_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_cmpswap_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_cmpswap_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_cond_sub_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_dec_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_dec_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_inc_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_inc_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_max_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_max_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_max_num_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_max_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_max_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_min_i32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_min_i64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_min_num_f32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_min_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_min_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_or_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_or_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_ordered_add_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_pk_add_bf16 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_pk_add_f16 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_sub_clamp_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_sub_u32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_sub_u64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_swap_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_swap_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_xor_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_atomic_xor_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_inv :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_addtid_b32 :ref:`vdst`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_b32 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_b96 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_block :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_hi_b16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_hi_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_hi_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_d16_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_i16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_i8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_addtid_b32 :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_b32 :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_i16 :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_i8 :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_u16 :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_lds_u8 :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_tr_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_tr_b64 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_u16 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_load_u8 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_addtid_b32 :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b128 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b16 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b32 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b64 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b8 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_b96 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_block :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_d16_hi_b16 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_store_d16_hi_b8 :ref:`vaddr`, :ref:`vsrc`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_wb :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` global_wbinv :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` VIMAGE ------ .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| image_atomic_add_flt :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_add_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_and :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_cmpswap :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_dec_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_inc_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_max_flt :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_max_int :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_max_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_min_flt :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_min_int :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_min_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_or :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_pk_add_bf16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_pk_add_f16 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_sub_uint :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_swap :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_atomic_xor :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_bvh64_intersect_ray :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_bvh8_intersect_ray :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_bvh_dual_intersect_ray :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_bvh_intersect_ray :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_get_resinfo :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load_mip :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load_mip_pck_sgn :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load_pck :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_load_pck_sgn :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_rsvd_atomic_umax_8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_rsvd_atomic_umin_8 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_store :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_store_mip :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_store_mip_pck :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_store_pck :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc` :ref:`dmask` :ref:`tfe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` VINTERP ------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_interp_p10_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` v_interp_p10_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` v_interp_p10_rtz_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` v_interp_p2_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` v_interp_p2_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` v_interp_p2_rtz_f16_f32 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` :ref:`clamp` :ref:`wait_exp` VOP1 ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_bfrev_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_ceil_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_ceil_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_ceil_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cls_i32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_clz_i32_u32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cos_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cos_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_ctz_i32_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f16_i16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f16_u16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_bf8 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_fp8 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_i32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_u32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_ubyte0 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_ubyte1 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_ubyte2 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f32_ubyte3 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f64_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f64_i32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_f64_u32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_floor_i32_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_i32_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_i32_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_nearest_i32_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_norm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_norm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_off_f32_i4 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_f32_bf8 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_f32_fp8 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_u32_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_u32_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_u32_u16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_exp_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_exp_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_floor_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_floor_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_floor_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_fract_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_fract_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_fract_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_exp_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_exp_i32_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_exp_i32_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_mant_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_mant_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_frexp_mant_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_log_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_log_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_mov_b16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_mov_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_mov_fed_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_mov_from_global_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_mov_to_global_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_movreld_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_movrels_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_movrelsd_2_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_movrelsd_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_nop :ref:`omod` :ref:`clamp` v_not_b16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_not_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_permlane64_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_pipeflush :ref:`omod` :ref:`clamp` v_rcp_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rcp_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rcp_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rcp_iflag_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_readfirstlane_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rndne_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rndne_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rndne_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rsq_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rsq_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_rsq_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sat_pk_u8_i16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sin_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sin_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sqrt_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sqrt_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_sqrt_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_swap_b16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_swap_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_swaprel_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_trunc_f16 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_trunc_f32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_trunc_f64 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` v_writelane_regwr_b32 :ref:`vdst`, :ref:`src0`::ref:`m` :ref:`omod` :ref:`clamp` VOP2 ---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_add_co_ci_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc`::ref:`m` :ref:`omod` :ref:`clamp` v_add_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_nc_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_nc_u64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_and_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_ashrrev_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_cndmask_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_rtz_f16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmaak_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`literal`::ref:`m` :ref:`omod` :ref:`clamp` v_fmaak_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`literal`::ref:`m` :ref:`omod` :ref:`clamp` v_fmaak_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`literal`::ref:`m` :ref:`omod` :ref:`clamp` v_fmac_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmac_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmac_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmamk_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`literal`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmamk_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`literal`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_fmamk_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`literal`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_illegal :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_ldexp_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_lshlrev_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_lshlrev_b64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_lshrrev_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_max_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_max_num_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_max_num_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_max_num_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_max_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_min_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_min_num_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_min_num_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_min_num_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_min_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_dx9_zero_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_hi_i32_i24 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_hi_u32_u24 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_i32_i24 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_u32_u24 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_mul_u64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_or_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_pk_fmac_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_co_ci_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_nc_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_nc_u64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_subrev_co_ci_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m`, :ref:`vcc`::ref:`m` :ref:`omod` :ref:`clamp` v_subrev_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_subrev_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_subrev_nc_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_xnor_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_xor_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` VOP3 ---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_add3_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_add_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_lshl_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_add_nc_i16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_nc_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_add_nc_u16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_alignbit_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_alignbyte_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_and_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_and_or_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_ashrrev_i16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_ashrrev_i64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_bcnt_u32_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_bfe_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_bfe_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_bfi_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_bfm_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cndmask_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cubeid_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cubema_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cubesc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cubetc_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_bf8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_fp8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_i16_i32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_norm_i16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_norm_i16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_norm_u16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_norm_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_u16_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_u16_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_pk_u8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_sr_bf8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_cvt_sr_fp8_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_div_fixup_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_fixup_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_fixup_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_fmas_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_fmas_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_scale_f32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_div_scale_f64 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_dot2_bf16_bf16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_dot2_f16_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_fma_dx9_zero_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_fma_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_fma_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_fma_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_ldexp_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_ldexp_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_lerp_u8 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_lshl_add_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_lshl_add_u64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_lshl_or_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_lshlrev_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_lshrrev_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_lshrrev_b64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_mad_co_i64_i32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_mad_co_u64_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_mad_i16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_mad_i32_i16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_mad_i32_i24 :ref:`vdst`, :ref:`src0`::ref:`m`, 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:ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_sub_nc_u16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_subrev_co_u32 :ref:`vdst`, :ref:`sdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_trig_preop_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_writelane_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` v_xad_u32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_xor3_b32 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m`, :ref:`src2`::ref:`m` :ref:`omod` :ref:`clamp` v_xor_b16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`src1`::ref:`m` :ref:`omod` :ref:`clamp` VOP3P ----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_dot2_f32_bf16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot2_f32_f16 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_f32_bf8_bf8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_f32_bf8_fp8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_f32_fp8_bf8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_f32_fp8_fp8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_i32_iu8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot4_u32_u8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot8_i32_iu4 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_dot8_u32_u4 :ref:`vdst`, :ref:`src0`, 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v_wmma_i32_16x16x16_iu4 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_wmma_i32_16x16x16_iu8 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` v_wmma_i32_16x16x32_iu4 :ref:`vdst`, :ref:`src0`, :ref:`src1`, :ref:`src2` VOPC ---- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_cmp_class_f16 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` v_cmp_class_f32 :ref:`vdst`, :ref:`src0`::ref:`m`, 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v_cmpx_u_f64 :ref:`vdst`, :ref:`src0`::ref:`m`, :ref:`vsrc1`::ref:`m` :ref:`omod` :ref:`clamp` VOPD ---- .. parsed-literal:: **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **SRC3** **SRC4** **SRC5** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_dual_add_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_add_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_add_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_add_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_add_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_add_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_cndmask_b32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc`, :ref:`literal` v_dual_cndmask_b32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc`, :ref:`literal` v_dual_cndmask_b32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vcc` v_dual_cndmask_b32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_cndmask_b32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_dot2acc_f32_bf16_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_dot2acc_f32_bf16_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_dot2acc_f32_bf16_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_dot2acc_f32_bf16_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_dot2acc_f32_bf16_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_bf16_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_dot2acc_f32_f16_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_dot2acc_f32_f16_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_dot2acc_f32_f16_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_dot2acc_f32_f16_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_dot2acc_f32_f16_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmaak_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc`, :ref:`literal` v_dual_fmaak_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`literal` v_dual_fmaak_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmaak_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmac_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_fmac_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmac_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmac_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_fmac_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmac_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_fmamk_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc`, :ref:`literal` v_dual_fmamk_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`literal` v_dual_fmamk_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_fmamk_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_max_num_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_max_num_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_max_num_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_max_num_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_max_num_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_max_num_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_min_num_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_min_num_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_min_num_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_min_num_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_min_num_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_mov_b32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mov_b32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mov_b32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0` v_dual_mov_b32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mov_b32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_mul_dx9_zero_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mul_dx9_zero_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mul_dx9_zero_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_mul_dx9_zero_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_dx9_zero_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_mul_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mul_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_mul_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_mul_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_mul_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_sub_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_sub_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_sub_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_sub_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_sub_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_add_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_add_nc_u32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_and_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_cndmask_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`vcc` v_dual_subrev_f32_x_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_dot2acc_f32_f16 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_fmaak_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_subrev_f32_x_fmac_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_fmamk_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1`, :ref:`literal` v_dual_subrev_f32_x_lshlrev_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_max_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_min_num_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_mov_b32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0` v_dual_subrev_f32_x_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_mul_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_sub_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_subrev_f32_x_subrev_f32 :ref:`vdstx`, :ref:`vdsty`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`srcy0`, :ref:`vsrcy1` VOPDX ----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_dual_add_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_cndmask_b32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`vcc` v_dual_dot2acc_f32_bf16 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_dot2acc_f32_f16 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_fmaak_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1`, :ref:`literal` v_dual_fmac_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_fmamk_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`literal`, :ref:`vsrcx1` v_dual_max_num_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_min_num_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_mov_b32 :ref:`vdstx`, :ref:`srcx0` v_dual_mul_dx9_zero_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_mul_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_sub_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` v_dual_subrev_f32 :ref:`vdstx`, :ref:`srcx0`, :ref:`vsrcx1` VOPDY ----- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| v_dual_add_nc_u32 :ref:`vdsty`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_and_b32 :ref:`vdsty`, :ref:`srcy0`, :ref:`vsrcy1` v_dual_lshlrev_b32 :ref:`vdsty`, :ref:`srcy0`, :ref:`vsrcy1` VSAMPLE ------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| image_gather4 :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_b :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_b_cl :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_b :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_b_cl :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_cl :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_l :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_lz :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_c_lz_o :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_cl :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` image_gather4_l :ref:`vdata`, :ref:`vaddr`, :ref:`rsrc`, :ref:`samp` :ref:`dmask` :ref:`tfe` :ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` 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:ref:`unorm` :ref:`lwe` :ref:`dim` :ref:`r128` :ref:`a16` :ref:`d16` :ref:`th` :ref:`scope` :ref:`nv` VSCRATCH -------- .. parsed-literal:: **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS** \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---| scratch_load_b128 :ref:`vdst`, :ref:`vaddr`, :ref:`saddr` :ref:`offset` :ref:`th` :ref:`scope` :ref:`nv` scratch_load_b32 :ref:`vdst`, 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